The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to metallization levels for integrated circuits and methods of fabricating metallization levels.
Metallization levels or layers of an integrated circuit provide connections between devices and components of the integrated circuits. Any one metallization level generally includes multiple conductive metallization lines, and metallization lines of one level may be connected by conductive vias to metallization lines of a higher or lower level. As integrated circuit devices continue to shrink, limitations of various fabrication techniques may restrict where conductive vias may be placed as well as how closely conductive vias may be placed together, restricting designs for particular metallization levels as well as the overall integrated circuit.